Memory devices are commonly used to store data in a wide variety of electronic systems, such as personal computers. Several distinct types of memory devices exist, such as dynamic random access memory (“DRAM”) devices, static random access memory (“SRAM”) devices, and read only memory devices (“ROM”). Each of these devices has specific attributes that make them particularly suited for various uses. DRAM devices, for example, have a significant advantage in being able to store data very compactly since significantly less circuitry is required to store each bit of data compared to, for example, SRAM devices. For this reason, DRAM devices are commonly used in applications where a large amount of data must be stored. For example, DRAM devices commonly serve as system memory in personal computers. DRAM devices store data in DRAM cells, each of which is capable of storing one bit of data. Each DRAM cell requires only a storage capacitor for storing either of two voltages corresponding to respective Boolean numbers, and an access transistor for selectively isolating the capacitor.
As with virtually any device in the field of electronics, attempts are continuously being made to improve their performance and lower their cost. Performance improvements in DRAM devices have generally focused on improving their speed, reducing the amount of power they consume, or increasing the amount of data they can store. Cost improvements have generally focused on reducing the size of DRAM devices because doing so allows more devices to be fabricated on each wafer, and manufacturing costs are heavily dependent on the cost to process each wafer. Reducing the size of DRAM devices generally involves making the circuitry used in the devices more compact by reducing the feature size as much as possible according to specific design rules. Making the circuitry used in DRAM devices more compact not only reduces the cost of DRAM devices, but it also has the effect of increasing their storage capacity, and, to some extent, increasing their operating speed.
With each generation of DRAM devices, their circuitry has become more compact. However, despite reductions in the minimum feature size of such circuitry, a limit to the amount of data that can be stored is always reached. Furthermore, the theoretical limit to reducing the feature size of semiconductor circuitry using existing technology may be near. DRAM devices could be made more compact if the capacitance of storage capacitors used in DRAM cells could be reduced. The voltage stored by a DRAM cell capacitor is sensed by the access transistor selectively coupling the capacitor to a digit line. However, the voltage stored by the capacitor is not simply transferred to the digit line because the digit line itself can have substantial capacitance. The actual change in the digit line voltage is proportional to the capacitance of the digit line compared to that of the capacitor. The voltage change ΔV is given by the formula:ΔV=(VC−VD)(CC/CC+CD),where VC is the voltage stored by the capacitor, VD is the voltage to which the digit line is precharged, CC is the capacitance of the memory cell capacitor, and CD is the capacitance of the digit line. It can be seen from the above formula that ΔV becomes smaller as CD becomes larger. For values of CD that are very much larger than CC, ΔV can approach zero. The magnitude of ΔV also becomes smaller if VC−VD becomes smaller. The voltage stored by the capacitor, VC, is usually either 0 volts or the supply voltage, VCC. The voltage to which the digit line is charged, VD, is usually one-half the supply voltage, or VCC/2. Therefore, the value of VC−VD is normally either VCC/2 (if VC is VCC) or −VCC/2 (if VC is 0 volts). In either case, since the magnitude of ΔV is directly proportional to the magnitude of VCC.
Regardless of whether ΔV becomes very small because the digit line capacitance CD has become very large or because the supply voltage VCC has become very small, a small value of ΔV can make it difficult to determine the voltage VC to which the capacitor was initially charged. It will then be difficult to read the value of a data bit stored in a DRAM memory cell.
It can also be seen from the above formula that ΔV can be increased by increasing CC and decreasing CD. In fact, ΔV can be made to approach the full difference between VC and VD, i.e, the digit line voltage can change to VC, by making CC much larger than CD. However, making CC significantly larger generally involves making memory cell capacitors significantly larger, thus making memory cells significantly less compact. This has the effect of reducing storage capacity and increasing cost. Making CD significantly smaller would also solve the problem. But long digit lines, which have large capacitances, are desired so that each digit line can be coupled to a large number of DRAM cells. Therefore, as a practical matter, the capacitance of DRAM cell capacitors cannot be reduced, thus precluding reductions in the size of DRAM cell capacitors.
One approach to storing data more compactly in DRAM devices that does not rely on reducing the feature size of DRAM circuitry is to store more than one bit in each DRAM cell. As mentioned above, the capacitor in each DRAM cells traditionally stores either of two voltages corresponding to respective Boolean numbers. Thus, each capacitor stores one bit of data. Proposals have been made to store two or more bits of data in each DRAM cell by storing one of four voltage levels in each DRAM cell capacitor. In general terms, a DRAM cell capacitor can store N bits of data by allowing the capacitor to store 2N different voltage levels. By allowing multiple bits of data to be stored in each DRAM cell, the storage capacity of a DRAM device can be greatly increased without adding a significant amount of additional circuitry.
Despite the voltage sensing problems inherent in using small capacitors and long digit lines, it is relatively easy to sense the voltage level stored in a DRAM cell capacitor when the capacitor is storing one of only two voltage levels. Conventional sense amplifiers for memory cells storing only a single bit must only sense whether the digit line voltage has increased or decreased from a voltage to which the digit line was precharged prior to the memory cell being coupled to the digit line. It is significantly more difficult to do so when the capacitor is storing four or more voltage levels. Conventional sense amplifiers for memory cells storing multiple bits must sense the degree to which the digit line voltage has increased or decreased from the digit line precharge voltage. Therefore, although storing multiple bits of data in each DRAM cell has significant advantages, doing so is not without significant problems. If the signal to be sensed, i.e., the change in the digit line voltage ΔV becomes very small, it can be masked by noise inherently present in the digit line. For example, if an access transistor connects a digit line to a capacitor that stores a larger voltage, the digit line voltage should increase. However, noise on the digit line can momentarily increase or decrease the digit line voltage, thereby causing the incorrect voltage to be sensed. This “signal-to-noise” ration problem has been a significant impediment to the practical implementation of multiple bit DRAM memory cells.
There is therefore a need for a DRAM architecture and method that allows the capacitance of DRAM cell capacitors to be reduced and/or allows multiple bits of data to be stored in each memory cell without unduly reducing storage capacity, reducing performance, or increasing cost.